###############################################################################
## @copyright Copyright (c) 2022 OnMicro Corp.
## @brief     UltraEmbedded SoC simulator environment.
## @author    wei.lu@onmicro.com.cn
## @license   SPDX-License-Identifier: Apache-2.0
###############################################################################
# Choice: [riscv, armv6m]
CPU         ?= riscv
# Choice: [rv32i, rv32i_spartan6, rv32im, rv32imsu]
RISCV_CORE  ?= rv32im

SOC          = ue_soc

# Test case list is src_c or in prebuilt/ue_soc/: [src_c, basic_putc_dscratch, coremark_v1.0]
CASE         = basic_putc_dscratch

# Simulator: [iverilog, verilator, vcs]
SIM          = iverilog
# Dump waveform: [off, on]
DUMP         = off

# Common verilog sources of UltraEmbedded SoC.
SRC_DIR     += ../../ip/soc/ultrae_generated/peripheral_axi4lite/src_v
SRC_DIR     += ../../ip/soc/ultrae_generated/axi4_axi4lite_conv/src_v

# RISC-V
ifeq ($(CPU),riscv)
  SRC_DIR      += ../../ip/cpu/ue_$(RISCV_CORE)/src_v
  SRC_DIR      += ../../ip/soc/ultrae_generated/riscv_tcm_wrapper/src_v
  SRC_DIR      += ../../ip/soc/ultrae_generated/dbg_bridge/src_v
  EXTRA_VFLAGS += CPU_SELECT_RISCV=1
else
  # Cortex M0
  SRC_DIR      += ../../ip/cpu/cortex_m0/src_v
  SRC_DIR      += ../../ip/soc/ultrae_generated/cortex_m0_wrapper/src_v
  EXTRA_VFLAGS += CPU_SELECT_ARMV6M=1
endif

# Test bench verilog sources and includes.
SRC_DIR     += ./src_v
INC_DIR      = ./inc_v

# Test Case stimulus file.
INC_DIR += ./$(CASE)
ifeq ($(CASE),coremark_v1.0)
  TIMEOUT = off
endif

# Testbench verilog file list.
ifeq ($(SIM),verilator)
SIM_FILELIST = ../src_cc/sim_main.cpp
endif

# Common logic to run simulator.
include ../common/Makefile.sim

# Generate program memory pattern to load by simulator.
vmem: | $(PROJECT_DIR)
ifeq ($(CASE),src_c)
	make -C src_c clean
	make -C src_c BASE_ADDRESS=0x0000 MEM_SIZE=0x10000 GCC_PREFIX=riscv-nuclei-elf- QUIET=yes
	riscv-nuclei-elf-objcopy -O srec src_c/build_riscv_c/c.elf $(PROJECT_DIR)/rom.srec
else
	riscv-nuclei-elf-objcopy -O srec ../../prebuilt/rv32im/$(CASE).elf $(PROJECT_DIR)/rom.srec
endif
	../../tool/python/srec2vmem.py -e l -i $(PROJECT_DIR)/rom.srec -o $(PROJECT_DIR)/rom.mem
